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| 7473 |
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Dual
Master-Slave J-K Flip-Flops
with Clear and Complementary Outputs
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POSITIVE
LOGIC
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For other 7400 series TTL IC
datasheets, CLICK
HERE
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7473 DIP Package
Pin Out
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7473 DATASHEET
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These Integrated Circuits contain two
independent J-K type positive-edge triggered flip flop circuits. A low
level at the preset or clear input pin resets the outputs
regardless of the levels of the other inputs, this lack of regard to
the clock cycle is called asynchronous. The values at J and K determine
the mode of operation for the flip flop. If both J K are high, then
with each clock pulse received, the outputs Q and Q' will toggle. The
chart in the image above fully details the behaviors of this mechanism.
JK Flip Flop circuits are important in building synchronous and
asynchronous counters, registers, frequency divide by two circuits,
etc.
JK Flip Flops can be cascaded to build counters of indefinite length,
however, in general, eventually propogation delays will limit the
complete circuits overall frequency rate. The 7473 discrete unit
typically can respond at between 15 and 25 megahertz. If you need
faster response times, liquid cooling might yield some interesting (and
definitely seldomly attempted) experiments.
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